View ICS843001AG-21T_1252964.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* One 3.3V LVPECL output pair and one LVCMOS output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 560MHz - 700MHz * Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV * RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.80ps (typical) Offset Noise Power 100Hz ............... -60.3 dBc/Hz 1kHz ............... -88.5 dBc/Hz 10kHz ............. -111.9 dBc/Hz 100kHz ............. -113.0 dBc/Hz * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843001-21 is a a highly versatile, low IC S phase noise LVPECL Synthesizer which can HiPerClockSTM generate low jitter reference clocks for a variety of communications applications and is a member of the HiPerClocks TM family of high performance clock solutions from ICS. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz cr ystal). The r ms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS843001-21 is packaged in a small 24-pin TSSOP package.
PIN ASSIGNMENT
VCCO_CMOS N0 N1 N2 VCCO_PECL Q0 nQ0 VEE VCCA VCC XTAL_OUT1 XTAL_IN1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_CLK VEE REF_OE M2 M1 M0 MR SEL1 SEL0 TEST_CLK XTAL_IN0 XTAL_OUT0
BLOCK DIAGRAM
3 N2:N0 SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 000 001 010 011 100 101 110 111 /1 /2 /3 /4 (default) /5 /6 /8 /10
ICS843001-21
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
Q0 nQ0
OSC
XTAL_OUT0
00
11
XTAL_IN1
OSC
XTAL_OUT1 TEST_CLK Pulldown
01
Phase Detector
VCO
10 01 00
10
000 001 010 011 100 101
M /18 /22 /24 /25 /32 (default) /40
MR M2:M0
Pulldown
3 REF_CLK OE_REF Pulldown
843001AG-21
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Description Output supply pin for LVCMOS output. Output divider select pins. Default /4. LVCMOS/LVTTL interface levels. Pulldown Output supply pin for LVPECL output. Differential output pair. LVPECL interface levels. Negative supply pin. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q0 to go low and the inver ted output nQ0 Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Feedback divider select pins. Default /32. LVCMOS/LVTTL interface levels. Pullup Pulldown Reference clock output enable. Default Low. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8, 23 9 10 11 12 13 14 15 16, 17 18 19, 20 21 22 24 Name VCCO_CMOS N0, N1 N2 VCCO_LVPECL Q0, nQ0 VEE VCCA VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 TEST_CLK SEL0, SEL1 MR M0, M1 M2 REF_OE REF_CLK Input Input Power Ouput Power Power Power Input Input Input Input Input Input Input Input Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Rout Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Output Impedance Test Conditions Minimum Typical 4 51 51 7 Maximum Units pF k k
843001AG-21
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Output Frequency (MHz) 74.25 74.25 74.1758245 155.52 77.76 622.08 311.04 156.25 125 62.5 100 150 75 106.25 212.5 159.375 187.5
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input Reference Clock 27 24.75 14.8351649 19.44 19.44 19.44 19.44 19.53125 25 25 25 25 25 26.5625 26.5625 26.5625 31.25 M Divider Value 22 24 40 32 32 32 32 32 25 25 24 24 24 24 24 24 18 N Divider Value 8 8 8 4 8 1 2 4 5 10 6 4 8 6 3 4 3 VCO (MHz) 594 594 593.4066 622.08 622.08 622.08 622.08 625 62 5 625 600 60 0 600 637.5 637.5 637.5 562.5 Application HDTV HDTV HDTV SONET SONET SONET SONET 10 GigE 1 GigE 1 GigE PCI Express SATA SATA Fibre Channel 1 4 Gig Fibre Channel 10 Gig Fibre Channel 12 Gig Ethernet
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER FUNCTION TABLE
Inputs M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 M Divider Value 18 22 24 25 32 40 Input Frequency Minimum 31.1 25.5 23.3 22.4 17.5 14.0 Maximum 38.9 31.8 29.2 28.0 21.9 17.5
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divide Value 1 2 3 4 5 6 8 10
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Reference XTAL0 XTAL1 TEST_CLK TEST_CLK PLL Mode Active Active Active Bypass
843001AG-21
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO + 0.5V 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO_PECL, _CMOS IEE ICCA ICCO_PECL, _CMOS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 170 11 8 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage SEL0, SEL1, OE_REF, Input MR, M0:M2, N0:N2 Low Voltage TEST_CLK TEST_CLK, SEL0, SEL1, Input OE_REF, MR, M0, M1, N2 High Current M2, N0, N1 Input Low Current TEST_CLK, SEL0, SEL1, OE_REF, MR, M0, M1, N2 M2, N0, N1 Test Conditions Minimum Typical 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V REF_CLK -5 -150 2.6 0.5 Maximum VCC + 0.3 0.8 1.3 150 5 Units V V V A A A A V V
IIH
IIL VOH
Output High Voltage; NOTE 1
VOL Output Low Voltage: Note 1 REF_CLK NOTE 1: Output terminated with 50 to VCCO _CMOS/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit Diagram".
843001AG-21
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO_PECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. 12 Test Conditions Minimum Typical Maximum 40 50 7 Units MHz MHz pF Fundamental
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT tPD t jit(O) fVCO t R / tF Parameter Output Frequency Propagation Delay, TEST_CLK to NOTE 1 REF_CLK RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range Output Rise/Fall Time LVPECL LVCMOS Test Conditions Minimum 56 2.3 622.08MHz (12kHz - 20MHz) 560 20% to 80% 20% to 80% 200 300 45 44 0.80 700 500 800 55 56 Typical Maximum 700 2.8 Units MHz ns ps MHz ps ps % %
LVPECL odc Output Duty Cycle LVCMOS NOTE 1: Measured from the VCC/2 of the input to VCCO_CMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz cr ystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843001AG-21
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 622.08MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
OC-12 Filter 622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.80ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Sonet OC-12 Filter to raw data OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
6
843001AG-21
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
1.655%
V CC , VCCA, VCCO_LVPECL
Qx
SCOPE
VCC , VCCA, VCCO_LVCMOS
Qx
SCOPE
LVPECL
nQx
LVCMOS
VEE
VEE
-1.3V0.165V
-1.65V5%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
nQ0 Q0
Phase Noise Plot
t PW
t
PERIOD
Noise Power
odc =
Phase Noise Mask
t PW t PERIOD
x 100%
f1
Offset Frequency
V
f2
CCO_LVCMOS
REF_CLK t PW
t
PERIOD
2
RMS Jitter = Area Under the Masked Phase Noise Plot
odc =
t PW t PERIOD
x 100%
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VCC 2
80% Clock Outputs
80% VSW I N G TEST_CLK
20% tR tF
20%
VCCO_LVCMOS
REF_CLK
t
PD
2
OUTPUT RISE/FALL TIME
843001AG-21
PROPAGATION DELAY
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843001-21 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p
ICS843001-21 ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
843001AG-21
www.icst.com/products/hiperclocks.html
8
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 125
FOUT FIN
Zo = 50
125
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843001AG-21
www.icst.com/products/hiperclocks.html
9
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843001-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 170mA = 589.05mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 589.05mW + 30mW = 619.05mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.619W * 65C/W = 110.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
24-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
843001AG-21
www.icst.com/products/hiperclocks.html
10
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843001AG-21
www.icst.com/products/hiperclocks.html
11
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843001-21 is: 4057
843001AG-21
www.icst.com/products/hiperclocks.html
12
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
843001AG-21
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843001AG-21 ICS843001AG-21T ICS843001AG-21LF ICS843001AG-21LFT ICS843001A21 ICS843001A21 ICS843001A21L ICS843001A21L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843001AG-21
www.icst.com/products/hiperclocks.html
14
REV. A OCTOBER 26, 2005
Integrated Circuit Systems, Inc.
ICS843001-21
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Description of Change Features Section - added Lead-Free bullet. Ordering Information table - added Lead-Free marking. Programmable N Output Divider Function Table - corrected heading from M Divide Value to N Divide value. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free note. Date 2/8/05
Rev A
Table T10 T3C
Page 1 14 3 9 10
A T10
10/26/05
843001AG-21
www.icst.com/products/hiperclocks.html
15
REV. A OCTOBER 26, 2005

▲Up To Search▲

Price & Availability of ICS843001AG-21T

	To Download ICS843001AG-21T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .